Glossary

Heterogeneous Compute (HC)
Any system that mixes two or more processor classes. HC lets you match each algorithm to the chip that runs it fastest or with the least power draw. I/ONX scales HC to full racks for AI training and inference.

Mix-Processor / Multi-Class Architecture
I/ONX’s design principle of using CPUs for orchestration, GPUs for massively parallel math, FPGAs for re-configurable logic and ASICs for fixed-function acceleration in the same node.

CPU / GPU / TPU / DPU
These stand for Central Processing Unit, Graphics Processing Unit, Tensor Processing Unit, and Data Processing Unit. TPUs and DPUs are ASICs

FPGA
Field-Programmable Gate Arrays are re-configurable silicon that can be rewired in the field to offload niche or emerging AI algorithms, enabling rapid adaptation without respinning ASICs.

ASIC
Application-Specific Integrated Circuits are a fixed-function chip (e.g., TPU, DPU) hard-wired for one class of workloads — extremely fast and power-efficient when matched to the right algorithm.

Composable Infrastructure
Hardware whose compute, memory and accelerators can be logically re-assembled on demand; Symphony’s “fully composable” backplane lets you re-brandish resources without tearing down racks.

Kernel Fusion
I/ONX’s Rust tool-chain that stitches many GPU/FPGA/ASIC kernels into one optimized super-kernel, slashing latency at scale.